Sunday, June 18, 2006

8:30 - 9:15

Bulent Celebi, CEO AirTies, Turkey Shift of product design to silicon suppliers is resulting in unhappy end users  (Invited keynote address)

9:20 - 9:30

Break

Session 8: Reconfigurable Systems (Invited Papers) Chair: Tughrul Arslan, University of Edinburgh, UK

9:30 - 9:55

Martin Margala, University of Rochester, USA Adaptable Architectures for Signal Processing Applications

9:55 - 10:20

Wim Vanderbauwhede, University of Glasgow, UK The Gannet Service-Based SoC: A Service-Level Reconfigurable Architecture

10:20  -10:45

Tanya Vladimirova and Xiaofeng Wu, University of Glasgow, UK On-Board Partial Run-Time Reconfiguration for Pico-Satellite Constellations

10:45 - 11:10

Sajid Baloch, Tughrul Arslan, University of Edinburgh, UK and Adrian Stoica, JPL, USA Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques

Session 6: Evolution of Digital Systems Chairs: Li-Shan Kang and Sanyou Zeng, Wuhan University , China

11:10 - 11:35

Lukas Sekanina, Brno University of Technology, Czech Republic Evolutionary Design of Digital Circuits: Where Are Current Limits?

11:35 - 11:45

Break

11:45 - 12:10

Jorge Peña, University of Lugano, Switzerland, Andres Upegui, and Eduardo Sanchez, EPFL, Switzerland Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware

12:10 - 12:35

Emanuele Stomeo, Tatiana Kalganova, and Cyrille Lambert, Brunel University, UK Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures

12:35 - 1:00

Wing On Fung, Tughrul Arslan, and Sami Khawam, University of Edinburgh, UK Genetic Algorithm Based Engine for Domain-Specific Reconfigurable Arrays

1:00 – 1:55

Lunch

1:55 - 2:20

Evangelos F. Stefatos, Tughrul Arslan, University of Edinburgh, UK, Didier Keymeulen, and Ian Ferguson, JPL, USA Towards the Integration of Drive Control Loop Electronics of the JPL/Boeing Gyroscope within an Autonomous Robust Custom-Reconfigurable Platform

2:20 – 2:45

Rui Liu (1), Sang-you Zeng (1), Lixin Ding, Wuhan University, China, Lishan Kang, Hui Li, Yuping Chen, Yong Liu, and Yueping Han, (1) China University of Geosciences, China An Efficient Multi-objective Evolutionary Algorithm for Combinational Circuit Design

Session 7: Reconfigurable Devices and Architecture Chair: Ahmet Ergodan, University of Edinburgh, UK

2:45 - 3:10

Mohsin A. Syed, EADS Astrium GmbH, Germany and Eberhard Schueler, PACT XPP Technologies AG, Germany Reconfigurable Parallel Computing Architecture for On-Board Data Processing

3:10 - 3:35

H. Fatih Ugurdag, Yahya Sahin, Onur Baskirt, Soner Dedeoglu, Sezer G. Ugurdag, and Yasar S. Kocak, Bahcesehir University, Turkey Population-Based FPGA Solution to Mastermind Game

3:35 - 4:00

Andy M. Tyrrell and Hong Sun, University of York, UK A Honeycomb Development Architecture for Robust Fault-Tolerant Design

4:00 - 4:25

H. J. Kadim, Liverpool JM University, UK State-Space Based Analytical Modelling for Real-Time Fault Recovery and Self-Repair with Applications to Biosensors

4:25 - 4:35

Break

Session 5: Morphogenetic and Cellular Adaptive Hardware Chair: Andy Tyrrell, University of York, UK

4:35 - 5:00

Gianluca Tempesti, Pierre-André Mudry, and Guillaume Zufferey, EPFL, Switzerland Hardware/Software Coevolution of Genome Programs and Cellular Processors

5:00 - 5:25

Gunnar Tufte, The Norwegian University of Science and Technology, Norway Gene Regulation Mechanisms Introduced in the Evaluation Criteria for a Hardware Cellular Development System

5:25 - 5:50

Justin Lee and Joaquin Sitte, Queensland University of Technology, Australia Gate-Level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs

5:50 – 6:15

Andres Upegui and Eduardo Sanchez, EPFL, Switzerland Evolving Hardware with Self-Reconfigurable Connectivity in Xilinx FPGAs

6:15 - 6:30

Concluding Remarks, Plans for the future